发布于 2026年8月12日 · 我们于 2026年9月02日 确认该职位仍然有效
Member Technical Staff / Principal RTL Design Engineer – 10 Years Define RTL architecture and design strategy for complex SoCs Own SoC-level integration, clocks, resets, and power intent Review and sign off RTL quality, lint/CDC, and low-power readiness Drive RTL methodologies, coding guidelines, and best practices Mentor RTL engineers and provide technical leadership Interface with customers and cross-functional stakeholders Tools & Skills Languages: Verilog, SystemVerilog Checks: Lint, CDC/RD…
